1. Field of the Invention
The present invention relates to solid-state image pickup devices, and more specifically to a technique of reducing noise occurring when reading is performed by a columnar signal-processing circuit provided for each pixel column of a solid-state image pickup device.
2. Description of the Related Art
Known amplifier solid-state image pickup devices include amplifier transistors provided in pixels thereof. Each amplifier transistor receives at a control electrode thereof a charge generated by a photoelectric converter, amplifies the charge, and outputs the amplified charge as a signal to a vertical output line, which is provided for each pixel column.
In some cases, vertical output lines are provided with columnar signal-processing circuits that process signals. Japanese Patent Laid-Open No. 2003-051989 discloses an exemplary configuration in which each columnar signal-processing circuit includes an amplifier circuit and a correlated-double-sampling (CDS) circuit. In this configuration, noise is reduced by inputting, to a differential amplifier, noise signals sequentially output from the columnar signal-processing circuits and signal components on which the noise signals are superimposed.
In CDS processing, a noise signal and a signal in which the noise signal is superimposed on an optical signal are sequentially sampled, and the difference between the two signals is calculated, whereby a signal in which the noise component is reduced is output. The circuit type varies with the finite difference method used, and the configuration disclosed in Japanese Patent Laid-Open No. 2003-051989 is only exemplary.
In the foregoing case where the pixels include amplifier transistors, the columnar signal-processing circuits are often configured to operate as followers. To make the columnar signal-processing circuits to operate as followers, a constant current needs to be supplied to the amplifier transistors. In this respect, Japanese Patent Laid-Open No. 2007-036916 discloses another exemplary configuration in which a constant current is supplied by providing each vertical output line with a metal-oxide-semiconductor (MOS) transistor configured to supply a constant current, i.e., a load MOS transistor.
The gates of the load MOS transistors provided for the respective vertical output lines are connected to a common wire. A constant voltage is supplied from a voltage supply circuit to the gates so that a desired constant current can be supplied thereto.
Referring to FIG. 6, the configuration disclosed in Japanese Patent Laid-Open No. 2007-036916 including the voltage supply circuit and the load MOS transistors provided for the vertical output lines will be described.
A unit pixel 600 includes an amplifier transistor. A constant current is supplied from a load MOS transistor 602 via a vertical output line 601 to the amplifier transistor of the pixel 600. A voltage is supplied to the gate of the load MOS transistor 602 via a voltage supply wire 603. The gate and the drain of a MOS transistor 604a are connected to the voltage supply wire 603. A constant current source 604b supplies a constant current to the MOS transistor 604a. The MOS transistor 604a and the constant current source 604b constitute a voltage supply circuit 604. The load MOS transistor 602, the MOS transistor 604a, and the constant current source 604b constitute a current mirror circuit.
In this configuration, image quality may be deteriorated because of noise generated by a mechanism described below.
Noise generation in the configuration shown in FIG. 6 will be described with reference to FIG. 7, which is a conceptual diagram showing operation timings in CDS processing. The horizontal axis represents time. The curve V603 represents the potential of the voltage supply wire 603. If the symbol “N” is used to denote a noise signal, and if the symbol “S” is used to denote a signal generated by photoelectric conversion, then FIG. 7 shows the respective timings at which the N signal and the S+N signal are sampled by a CDS circuit. For example, in the case of Japanese Patent Laid-Open No. 2003-051989, hold capacitors 23 and 24 shown in FIG. 1 thereof hold signals at such timings.
Referring to FIG. 7, an examination by the present inventors has revealed that the potential of the voltage supply wire 603 shows temporal changes. This is because of noise generated by a voltage generator of the voltage supply circuit 604.
The voltage supply circuit 604 includes the transistor 604a. It is generally known that, when a transistor circuit operates, the transistor circuit generates so-called 1/f noise, whose power spectrum is proportional to the reciprocal of a frequency f, and so-called thermal noise, whose power spectrum is constant with respect to the frequency and is proportional to the output resistance. These kinds of noise cause the temporal changes in the potential of the voltage supply wire 603.
In the operation of a solid-state image pickup device, the time lag between N signal sampling and S+N signal sampling is usually about several microseconds. The frequency band of the noise described above is a band of about several thousand kilohertz. Let us suppose that the thermal noise component in the band of several thousand kilohertz ranges from a few tens of microvolts to several hundred microvolts. Even if the potential of the voltage supply wire is designed to be 800 mV, for example, the temporal change caused by the noise in the frequency band of several thousand kilohertz ranges from a few tens of microvolts to several hundred microvolts, with the average potential of 800 mV at the center of the range.
Accordingly, as shown in FIG. 7, the potential of the voltage supply wire 603 at time T1 when the N signal is sampled differs from the potential of the voltage supply wire 603 at time T2 when the S+N signal is sampled, by a level equivalent to the aforementioned range. Moreover, the potential randomly changes at every sampling. As the potential of the voltage supply wire 603 increases, the current of the load MOS transistor 602 also increases, and accordingly the output of a source-follower circuit constituted by the amplifier transistor, which is a MOS transistor, and the load MOS transistor 602 increases. Because the transistors in this case are assumed to be negative-channel MOS (NMOS) transistors, an increase in the output of the source-follower circuit means a decrease in the source potential. The relationship between the change in the amperage flowing through the load MOS transistor 602 and the gate potential is also described on the assumption that the transistors are NMOS transistors.
It is desirable that the difference between the potential of the vertical output line at the time of N signal sampling and the potential of the vertical output line at the time of S+N signal sampling becomes equal to the signal amount excluding the noise component. However, for the reason described above, a randomly changing voltage is sometimes superimposed on a signal that has undergone CDS processing. Such noise is generated separately from pixel noise attributed to the pixel, and is hereinafter called “horizontal noise.”
It is known that, in an amplifier solid-state image pickup device including two-dimensionally arranged pixels, signals of the pixels are read in time series by a vertical scanning circuit for each group of pixels included in a single row of the pixel array at a time. Therefore, the above-described noise component randomly varies with pixel row. Accordingly, such a noise component, which varies from row to row, appears in a display image as a change in the image level for each horizontal row.
A restricting factor that makes it difficult to reduce the noise of the voltage generator included in the voltage supply circuit 604 shown in FIG. 6 will be described.
It is desirable to set the conductance of the load MOS transistor 602 to a small value. This is because the variation in the constant current can be made smaller than the variation among the threshold voltages of the respective load MOS transistors 602. Specifically, when the gate length and the gate width of the load MOS transistor 602 are denoted by L and W, respectively, it is only necessary to make W/L small by setting a large value for L. In this case, if the MOS transistor 604a is made to be of the same size as the load MOS transistor 602, the output resistance of the voltage supply circuit 604 becomes large. This increases the noise in the several thousand kilohertz band. To reduce the output resistance of the voltage supply circuit 604, the number of MOS transistors 604a that are connected in parallel can be increased. Such a configuration, however, requires an increase in the amperage of the current of the constant current source 604b in correspondence with the number of transistors 604a to be connected in parallel. Considering the current consumption, the number of transistors 604a to be connected in parallel cannot be increased easily.
The above description concerns a mechanism of generation of horizontal noise due to changes in the gate potential of a load MOS transistor configured to supply a current to an amplifier transistor included in a pixel. More generally speaking, the mechanism can be applied to a case where a common voltage is supplied to columnar circuits each provided for a single column or a group of columns, such as signal-processing circuits connected to respective pixel columns. This means that, if a change in the potential of the voltage supply wire changes the level of a signal that is processed by the signal-processing circuit, there is a possibility that a mechanism similar to the one described above causes horizontal noise. For example, in a case of an amplifier circuit, functioning as a signal-processing circuit, configured to amplify a pixel signal, a change in the potential of the voltage supply wire via which a reference voltage is supplied to the amplifier circuit may also cause horizontal noise.
To summarize, a known amplifier solid-state image pickup device in which CDS processing is performed has a problem in that the noise of a voltage supply circuit configured to supply a voltage to a reading circuit may cause horizontal noise. Particularly, it is difficult to reduce the noises of the voltage supply circuit and a voltage supply wire connected to the gates of load MOS transistors provided to vertical output lines.